Embodiments of the present invention relates to a thin film transistor liquid crystal display (TFT-LCD) array substrate and a manufacturing method thereof.
TFT-LCDs belong to an important type of flat panel displays (FPDs). FIG. 1 is a schematic plan view of a conventional TFT-LCD array substrate. As shown in FIG. 1, the array substrate comprises a gate line 1, a data line 2, a thin film transistor (TFT) 3 and a pixel electrode 4. The gate line 1 is provided horizontally on a transparent substrate 11, the data line 2 is provided vertically on the substrate 11, and the TFT 3 is provided at an intersection of the gate line 1 and the data line 2. The TFT 3 is an active switch element.
FIG. 2 is a cross-sectional view taken along a line A-A in FIG. 1. As shown in FIG. 2, the array substrate comprises a gate electrode 12, a gate insulating layer 13, a semiconductor layer 14, a doped semiconductor layer 15, a source electrode 16, a drain electrode 17, and a passivation layer 18. The above structures are all provided on the substrate 11. The gate electrode 12 and the gate line 1 are formed integrally, the source electrode 16 and the data line 2 are formed integrally, and the drain electrode 17 and the pixel electrode 4 are connected with each other through a via hole formed in the passivation layer. When the gate line 1 is input with an “ON” signal, an active layer (including the stack of the semiconductor layer 14 and the doped semiconductor layer 15) becomes conductive, a data signal over the data line 2 is transmitted from the source electrode 16 to the drain electrode 17 through a TFT channel 19, and the data signal is finally transmitted to the pixel electrode 4. The pixel electrode 4 applied with the data signal generates an electrical field together with a common electrode (not shown), which is provided on the array substrate or a color filter substrate facing the array substrate, depending on the type of the TFT-LCD, so as to drive the rotation of the liquid crystal material.
Currently, a TFT-LCD is manufactured by forming structure patterns with patterning processes. Each patterning process comprises steps such as applying photoresist, exposing and developing the photoresist, etching with a photoresist pattern, and removing remaining photoresist. The etching process may comprise a dry etching method or a wet etching method. Therefore, the times of the patterning processes can be used to evaluate the complexity of the manufacturing method of a TFT-LCD array substrate, and reducing the times of the patterning processes means reducing manufacturing cost.
To reduce the number of the employed patterning process, the combination of a dual tone masking process and a lifting-off process is typically applied. A dual tone mask can adjust the amount of penetrating light across the mask and thus selectively control the heights across the formed photoresist pattern. With the photoresist pattern, more than one etching process can be performed.
For example, when the combination of a dual tone masking process and a lifting-off process is used to form a pixel electrode, a faultage or step is formed at the edge of the pixel electrode pattern when depositing the transparent conductive layer so that the subsequent lifting off process can be implemented. An under cut (a bevel edge inclining inwardly) can be formed along the edges of the photoresist pattern when etching the passivation layer. After forming the under cut of the photoresist pattern, the transparent conductive layer deposited on the photoresist pattern fauns a faultage at the under cut so as to expose the under cut of the photoresist pattern. At this time, the photoresist pattern together with the transparent conductive layer on the photoresist pattern can be lifted off from the under cut so as to obtain the pattern of the pixel electrode. This method is called as lifting-off process.
However, an ashing process is carried out after the under cut is formed when the second insulating layer is etched, thus it is difficult to maintain the under cut of the photoresist pattern. In addition, the problem of forming the under cut to different extents (i.e., the different degrees of inward inclination of the bevels) may occur. Therefore, the possibility of fault lifting-off increases, and the product yield decreases accordingly. In addition, when the ashing process is carried out on photoresist, the transparent conductive layer may be contaminated, which brings about a high defective ratio and corresponding complicated treatment procedures.